Samsung Electronics has developed a technology that applies a vertical stacking structure, such as high bandwidth memory (HBM), to non-memory logic semiconductors and reduces gate pitch to the smallest in the industry. The technology is expected to overcome the limits of advanced process scaling and further enhance high-performance semiconductors for artificial intelligence (AI).

Samsung Electronics Semiconductor R&D Center announced on the 17th that it presented a vertically stacked transistor with a gate pitch of 42nm (nanometers; 1nm is one billionth of a meter) at the VLSI Symposium, a global semiconductor conference held in Hawaii, United States. Gate pitch refers to the horizontal length of a single transistor, the channel through which electricity flows in a semiconductor. Until now, the minimum gate pitch in this field was 48nm. VLSI is regarded, along with IEDM and ISSCC, as one of the world’s three major semiconductor conferences.

To date, vertically stacked semiconductor structures have mainly been commercialized in the memory sector. HBM in DRAM and V-NAND in NAND flash are representative examples. Samsung Electronics has advanced a technology that enables such a stacking structure to be applied to logic semiconductors such as graphics processing units (GPUs) and central processing units (CPUs).

Samsung Electronics assessed that “the industry has reached a turning point where the question that hit a limit in planar structures—‘how small can it be made?’—is being replaced by ‘how high can it be stacked?’.”

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